More than 20 years of wafer solder bumping, Cu pillar bumping and flip chip in package ( CSP, BGA and SiP) assembly experience
Broad expertise in highly integrated 2D and 3D System in Package applications including FO-WLP and embedded component in laminate technology variants
Extensive experience in NPI and qualification of Fan-Out WLP / PLP packaging technologies for automotive and life sustaining medical electronics applications to highly demanding quality and reliability specifications
Supported industry and consortia development efforts in embedded components in laminate technologies over the past 2 decades including defining design rules for embedded die redistribution requirements and infrastructure building
Extensive process integration involvement with customers, OEMs, foundries and OSATS to enable novel wafer level packaging solutions for MEMS, image sensor and fluidic device applications
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